1. Field of the Invention
The present invention relates to a method and an apparatus for verifying a specification of a subject of design such as hardware and software.
2. Description of the Related Art
Due to an increased scale and multi-functionality of software and hardware, verification work for confirming that a system operates properly has been becoming more and more complicated. 50% of work in software development and 70% to 80% of work in hardware development are such verification work. Especially, work repeated for correction due to faults in specifications is very common, and 75% of work for redesigning in large-scale integration (LSI) design is due to faults in specifications.
The verification work mentioned above requires two kinds of verification work. One is to confirm that the system is designed correctly, and the other is to confirm that the system is implemented correctly. A conventional technology for the verification work basically focuses on confirmation of correct implementation. As for confirmation of correct design, verification is performed on the specifications by visual inspection since the specifications are usually written in a natural language. Methods of verification of specifications are disclosed in, for example, Japanese Patent Laid-Open Publication Nos. 2001-202398, 2004-78501, H8-6778, H6-75761, and H8-16625.
However, if the specifications are verified by the visual inspection, it is impossible to eliminate such problems as ambiguities, inconsistencies, omissions, and errors. Consequently, some of the problems may be reflected in implementation to lead to a faulty design. Thus, design quality is deteriorated. Removal of the faulty design at a stage of implementation requires considerable time and effort, resulting in prolonging a design period and increasing a workload on a designer.
In the apparatus for supporting verification of a specification disclosed in Japanese Patent Laid-Open Publication No. 2001-202398, a use case is not used. Consequently, the specifications are not verified in terms of function. As a result, if an error is included in a function, the error cannot be removed. Thus, the design quality can be deteriorated.
In an apparatus for supporting design and a method of evaluating a design result disclosed in Japanese Patent Laid-Open Publication No. 2004-78501, only whether requirement is satisfied is checked, and such problems as ambiguities, inconsistencies, omissions, and errors cannot be eliminated from the specifications. Thus the design quality can be deteriorated.
In the apparatus for verifying a specification of software disclosed in Japanese Patent Application Laid-Open Publication No. H8-6778, although omissions in a state of the specifications are checked, omissions or inconsistencies in an event flow from an external device are not checked. Therefore, it is impossible to completely eliminate such problems as ambiguities, inconsistencies, omissions, and errors. Thus, the design quality can be deteriorated.
In apparatus for verifying a specification disclosed in Japanese Patent Application Laid-Open Publication No. H6-75761, the specifications should be written in an algebraic language. However, specifically how the specifications are written is unclear, and it is difficult to actually write entire specifications in the algebraic language. Consequently, a workload on a designer increases.
In an apparatus for verifying execution of a specification disclosed in Japanese Patent Application Laid-Open No. H8-16625, the specification should be converted into a model. This increases a number of processes, resulting in an increased design period and an increased workload on a designer.
Thus, in the conventional technologies described above, it is impossible to completely eliminate the problems, such as ambiguities, inconsistencies, omissions, and errors, from the specifications. As a result, the design quality is deteriorated, and the verification period and the workload on the designer increase.